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iWarp
Gross T., O’Hallaron D., MIT Press, Cambridge, MA, 1998. Type: Book (9780262071833)
Date Reviewed: Nov 1 1998

The iWarp is an experimental parallel computer system that was designed and built jointly by Carnegie Mellon University and Intel Corporation in the mid-to-late 1980s under the guidance of H. T. Kung. The iWarp is specifically designed for systolic computation, a pipeline-like style of parallel execution. It featured integrated support for fine-grained communication, and a long instruction word (LIW) instruction set. Interestingly, LIW is now one of the major ingredients in Merced/EPIC, Intel and Hewlett-Packard’s forthcoming processor architecture.

The machine was intended for signal processing applications. It offered a cumulative bandwidth of 2 GByte/s on a 64-node system, and computed the fastest fast Fourier transform of its class. The project was one of the first to experiment with a close integration of communication with computation, delivering high communication bandwidth to applications. (For example, a word-transfer to neighboring nodes takes two clock cycles, the same as a memory access.) The project also made contributions to flow control schemes and to compiler technology for systolic and LIW architectures. Some other research projects focusing on tight integration of communication into the processor are Alewife, J-machine, Monsoon, and Star-T, all at MIT, but these projects did not target systolic computing.

The book provides a detailed technical overview of the iWarp project. It describes the complete iWarp system, from instruction-level parallelism to final parallel applications. The chapters cover the following topics: an overview of iWarp, logical communication channels, pathways (a permanent form of logical channels), the processing agent, the iWarp parallel system, the program development tool chain, compilers, the runtime system, communication styles, communication operations, and applications. The book is well written. The technical chapters provide a wealth of detail, with many diagrams and code snippets. The authors thoroughly document the project and the innovative features of its design. Each chapter ends with a summary, so readers do not get lost in the many details.

In addition to mentioning the accomplishments of the project, the authors identify some of its weaknesses and areas for improvement, both in the design and in the project management. (Significantly, the book’s front cover features an elephant jumping through a hoop.)

Systolic machines support fine-grain, global communication patterns. Today’s high-performance non-uniform memory access (NUMA) architectures work well with coarser-grain communication, emphasizing locality. Systolic machines are far from today’s mainstream designs. With today’s convergence to NUMA designs, it is all the more refreshing to come across an account of ideas that are so far off the beaten track.

The book is targeted to researchers working in parallel computer architecture. It provides a comprehensive, well-written, detailed overview of a unique research project.

Reviewer:  Aske Plaat Review #: CR121827 (9811-0857)
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Parallel Architectures (C.1.4 )
 
 
Instruction Set Design (C.0 ... )
 
 
Microcomputers (C.5.3 )
 
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