This paper analyzes the limitations of traditional network-on-a-chip (NoC or NOC) architectures and proposes a modified architectural paradigm called WNoC. NOC is a communication architecture that defines pathways between “intellectual property (IP) cores in a system on a chip (SoC)” [1]. It uses a combination of synchronous, asynchronous, or no clocks to improve the scalability of SoCs, as well as power efficiency. In NoCs, “a high level of parallelism is achieved because all links in the NoC can operate simultaneously on different data packets” [1]. The wires in the links of the NoC are shared by many signals. As wires are shared, and the number of cores per chip grows, there are resulting scalability and latency issues.

In the proposed WNoC, all cores share a single wireless broadband channel. This ensures low latency and ordered delivery of multicast traffic, and complements wire-line NoCs in communication flows. The feasibility of WNoC is assessed as a function of the system size, the channel capacity, with respect to wire-line NoCs.

The paper discusses an experimental WNoC framework, including simulated architecture, traffic generation, wireless communication models, network architectures, and performance metrics. Results have been analyzed for a range of N (number of nodes), C (channel capacity), and &bgr; (broadcast percentage), along with sensitivity analysis, performance, and implementation costs. The authors conclude that improvement is more noticeable as the system size increases.

This well-written paper has 69 references and would interest NoC researchers.